1. Field of the Invention
The present invention relates to a memory array, and in particular to a cost saving electrically-erasable-programmable read-only memory (EEPROM) array.
2. The Prior Arts
Presently, in the semiconductor industry, Complementary Metal Oxide Semiconductor (CMOS) manufacturing process has become an ordinary manufacturing method for Application Specific Integrated Circuit (ASIC). With the rapid progress and development of the computer and information products, Flash memory and electrically-erasable-programmable read-only memory (EEPROM) have been widely utilized in various electronic products for its non-volatile memory capability of being electrically programmable and erasable, such that data stored thereon will not be lost, even when its power supply is turned off.
In general, a non-volatile memory is programmable, and the memory stores charges in order to change the gate voltage of a transistor in the memory, or the memory will not store charges, such that the gate voltage remains unchanged as the original gate voltage of the transistor in the memory. For an erasure operation, the charges stored in the non-volatile memory are removed, such that the gate voltage of the transistor in the memory will return to its original value. As to the architecture of the Flash Memory at present, though it has the advantages of low cost and occupying small area, yet it can only support writing and erasing of large blocks of memory, and it is not able to perform writing and erasing for a specific bit memory cell, thus it is not quite convenient in application. In addition, for the architecture of an electrically-erasable-programmable read-only memory (EEPROM), it is capable of byte-writing memory on a byte basis, therefore, it is much more convenient in application as compared with the Flash Memory. Refer to FIGS. 1 & 2 for a circuit diagram of a bit memory cell, and a cross section view of bit memory cell of the prior art respectively. As shown in FIGS. 1 and 2, each memory cell contains: two transistors, wherein, one of them is a memory transistor 10, and the other is a switching transistor 12; and a capacitor 13, disposed on top of the memory transistor 10, hereby forming a poly-silicon memory cell. The problem of this kind of memory structure is that, the area required is larger than that of the flash memory; also, in performing bit erasing of memory, the memory cells not being selected must be isolated with transistors, thus raising the production cost.
Therefore, presently, the performance and cost effectiveness of the EEPROM are not quite satisfactory, and it has much room for improvement.